What is the (Appendix C) as mentioned throughout the assignment?

What is the (Appendix C) as mentioned throughout the assignment?
Portfolio Prompt Four – Computer Architecture and Machine Language Background Wow, the last four weeks you have taken in a great deal of information. You have learned about computers from their inception through the smallest of parts (transistors, bits, gates, etc.). This week is the final week of studying the machine itself. The work you did this week focused on the CPU and Machine Language. The CPU, using the machine cycle (fetch, decode, execute), can process instructions based on the language for the given CPU. For this module we are using a small language taken from a text book [1]. It is the language you have used in class. You will use that language and the machine cycle to complete this week’s prompt. The Prompt Given the machine language document and the CPU work sheet attached to this prompt, complete the following: Translate the following instructions from English into the machine language given with this assignment (Appendix C). a. LOAD register 6 with the hexadecimal value 77. b. LOAD register 7 with the contents of memory cell 77. c. JUMP to the instruction at memory location 24 if the contents of register 0 equals the value in register A. d. ROTATE register 4 three bits to the right. e. AND the contents of registers E and 2 leaving the result in register 1. a. b. c. d. e. The following are instructions written in the machine language given with this assignment (Appendix C). Translate them into English. a. 7123 b. 40E1 c. A304 d. B100 e. 2BCD a. b. c. d. Section of main memory Address Contents e. Use, and turn in the CPU Worksheet for the following problems: Suppose the memory cells at addresses 00 through 05 in the machine described in Appendix C contain the following bit patterns: Address Contents 00 12 01 02 02 32 03 42 04 C0 05 00 When answering the following questions, assume that the machine starts with its program counter equal to 00. Translate the instructions that are executed into English. What bit pattern is in the memory cell at address 42 when the machine halts? What bit pattern is in the program counter when the machine halts? Suppose the memory cells at addresses 00 through 0D in the machine described in Appendix C contain the following bit patterns: Address Contents 00 20 01 04 02 21 03 01 04 40 05 12 06 51 07 12 08 B1 09 0C 0A B0 0B 06 0C C0 0D 00 Assume that the machine starts with its program counter containing 00. What bit pattern will be in register 0 when the machine halts? What bit pattern will be in register 1 when the machine halts? What bit pattern is in the program counter when the machine halts? [1] G. G. Brookshear and J. G. Brookshear, Computer science: an overview. Addison-Wesley Longman Publishing Co., Inc., 2002.
What is the (Appendix C) as mentioned throughout the assignment?
The first digit in each machine language instruction is the op -code. The following 3 digits are mapped to the instruction with the variables RXY, ORS, RST, or ROX. 1 RXY LOAD the register R w/ bit pattern found in the memory cell whose address is XY. (Example: 14A3 would cause the contents of the memory cell locat ed at address A3 to be placed in register 4). 2 RXY LOAD the register R w/ bit pattern XY. (Example: 20A3 would cause the value A3 to be placed in register 0). 3 RXY STORE the bit pattern found in register R in the memory cell whose address is XY. (Example: 35B1 would cause the contents of register 5 to be placed in the memory cell whose address is B1). 4 ORS MOVE the bit pattern found in register R to register S. (Example: 40A4 would cause the contents of register A to be copied into register 4) . 5 RST ADD the bit patterns in registers S & T as though they were two’s complement representations & leave the result in register R. (Example: 5726 would cause the binary values in registers 2 and 6 to be added and the sum placed in register 7). 6 RST ADD the bit patterns in registers S and T as though they represented values in floating -point notation and leave the floating -point result in register R. ( Example: 634E would cause the values in registers 4 and E to be added as floating -point valu es and the result to be placed in register 3). 7 RST OR the bit patterns in registers S and T and place the result in register R. (Example: 7CB4 would cause the result of ORing the contents of registers B and 4 to be placed in register C). 8 RST AND the bit patterns in register S and T and place the result in register R. (Example: 8045 would cause the result of ANDing the contents of registers 4 and 5 to be placed in register 0). 9 RST EXCLUSIVE OR the bit patterns in registers S and T and place t he result in register R. (Example: 95F3 would cause the result of EXCLUSIVE ORing the contents of registers F and 3 to be placed in register 5). A R0X ROTATE the bit pattern in register R one bit to the right X times. Each time place the bit that start ed at the low -order end at the high -order end. (Example: A403 would cause the contents of register 4 to be rotated 3 bits to the right in a circular fashion). B RXY JUMP to the instruction located in the memory cell at address XY if the bit pattern in register R is equal to the bit pattern in register number 0. Otherwise, continue with the normal sequence of execution. (The jump is implemented by copying XY into the program counter during the execute phase.) (Example: B43C would first compare the cont ents of register 4 with the contents of register 0. If the two were equal, the pattern 3C would be placed in the program counter so that the next instruction executed would be the one located at that memory address. Otherwise, nothing would be done and pro gram execution would continue in its normal sequence). C 000 HALT execution. (Example: C000 would cause program execution to stop). Brookshear, G. G., & Brookshear, J. G. (2002). Computer science: an overview . Addison -Wesley Longman Publishing Co., Inc. Retrieved from http://dl.acm.org/citation.cfm?id=549236
What is the (Appendix C) as mentioned throughout the assignment?
CS 160 CPU Worksheet Name:______________________ Central Processing Unit Main Memory Registers Program Counter Address Address 00 01 Bus 02 03 —– —– —– 04 05 Instruction Register 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Central Processing Unit Main Memory Registers Program Counter Address Address 00 01 Bus 02 03 —– —– —– 04 05 Instruction Register 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Central Processing Unit Main Memory Registers Program Counter Address Address A4 A5 Bus A6 A7 —– —– —– A8 A9 Instruction Register AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 C3 Central Processing Unit Main Memory Registers Program Counter Address Address 00 01 Bus 02 03 —– —– —– 04 05 Instruction Register 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Central Processing Unit Main Memory Registers Program Counter Address Address 00 01 Bus 02 03 —– —– —– 04 05 Instruction Register 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Central Processing Unit Main Memory Registers Program Counter Address Address A4 A5 Bus A6 A7 —– —– —– A8 A9 Instruction Register AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 C3 Central Processing Unit Main Memory Registers Program Counter Address Address A4 A5 Bus A6 A7 —– —– —– A8 A9 Instruction Register AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 C3 Central Processing Unit Main Memory Registers Program Counter Address Address 00 01 Bus 02 03 —– —– —– 04 05 Instruction Register 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Central Processing Unit Main Memory Registers Program Counter Address Address 00 01 Bus 02 03 —– —– —– 04 05 Instruction Register 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Central Processing Unit Main Memory Registers Program Counter Address Address 00 01 Bus 02 03 —– —– —– 04 05 Instruction Register 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Central Processing Unit Main Memory Registers Program Counter Address Address 00 01 Bus 02 03 —– —– —– 04 05 Instruction Register 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Central Processing Unit Main Memory Registers Program Counter Address Address 00 01 Bus 02 03 —– —– —– 04 05 Instruction Register 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Central Processing Unit Main Memory Registers Program Counter Address Address 00 01 Bus 02 03 —– —– —– 04 05 Instruction Register 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Central Processing Unit Main Memory Registers Program Counter Address Address 00 01 Bus 02 03 —– —– —– 04 05 Instruction Register 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Central Processing Unit Main Memory Registers Program Counter Address Address 00 01 Bus 02 03 —– —– —– 04 05 Instruction Register 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Central Processing Unit Main Memory Registers Program Counter Address Address 00 01 Bus 02 03 —– —– —– 04 05 Instruction Register 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Central Processing Unit Main Memory Registers Program Counter Address Address 00 01 Bus 02 03 —– —– —– 04 05 Instruction Register 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Central Processing Unit Main Memory Registers Program Counter Address Address 00 01 Bus 02 03 —– —– —– 04 05 Instruction Register 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Central Processing Unit Main Memory Registers Program Counter Address Address 00 01 Bus 02 03 —– —– —– 04 05 Instruction Register 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Central Processing Unit Main Memory Registers Program Counter Address Address 00 01 Bus 02 03 —– —– —– 04 05 Instruction Register 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Central Processing Unit Main Memory Registers Program Counter Address Address 00 01 Bus 02 03 —– —– —– 04 05 Instruction Register 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F